Imaging devices, including charge coupled devices (CCD) and complementary metal oxide semiconductor (CMOS) sensors have commonly been used in photo-imaging applications.
Typically, a digital imager circuit includes a focal plane array of pixel cells, each one of the cells including a photosensor, e.g. a photogate, a photoconductor, or a photodiode. A CMOS imager is one such digital imager circuit and includes a readout circuit connected to each pixel cell in the form of an output transistor. The photosensor converts photons to electrons which are typically transferred to a floating diffusion region, connected to the gate of a source follower output transistor. A charge transfer device can be included as well and may be a transistor for transferring charge from the photosensor to the floating diffusion region. Imager cells also typically have a transistor for resetting the floating diffusion region to a predetermined charge level prior to charge transference. The output of the source follower transistor is gated as an output signal by a row select transistor.
Exemplary CMOS imaging circuits, processing steps thereof, and detailed descriptions of the functions of various CMOS elements of an imaging circuit are described, for example, in U.S. Pat. No. 6,140,630 to Rhodes, U.S. Pat. No. 6,376,868 to Rhodes, U.S. Pat. No. 6,310,366 to Rhodes et al., U.S. Pat. No. 6,326,652 to Rhodes, U.S. Pat. No. 6,204,524 to Rhodes, and U.S. Pat. No. 6,333,205 to Rhodes. The disclosures of each of the forgoing are hereby incorporated by reference in their entirety.
FIG. 1 illustrates a block diagram of a CMOS imager device 308 having a pixel array 300 with each pixel cell being constructed as described above. Pixel array 300 comprises a plurality of pixels arranged in a predetermined number of columns and rows (not shown). The pixels of each row in array 300 are all turned on at the same time by a row select line, and the pixels of each column are selectively output by respective column select lines. A plurality of row and column lines is provided for the entire array 300. The row lines are selectively activated by a row driver 210 in response to a row address decoder 220. The column select lines are selectively activated by a column driver 260 in response to a column address decoder 270. Thus, a row and column address is provided for each pixel. The CMOS imager device 308 is operated by a timing and control circuit 250, which controls address decoders 220, 270 for selecting the appropriate row and column lines for pixel readout. The control circuit 250 also controls the row and column driver circuitry 210, 260 such that these apply driving voltages to the drive transistors of the selected row and column lines. The pixel column signals, which typically include a pixel reset signal (Vrst) and a pixel image signal (Vsig), are read by a sample and hold circuit 261 associated with the column device 260. A differential signal (Vrst−Vsig) is produced by differential amplifier 262 for each pixel that is amplified and digitized by analog to digital converter 275 (ADC). The analog-to-digital converter 275 supplies the digitized pixel signals to an image processor 280, which forms and outputs a digital image.
P-n-p photodiodes are a type of photosensor sometimes used in CMOS pixel cells. In a CMOS imager, when incident light strikes the surface of a photodiode, electron/hole pairs are generated in the p-n junction of the photodiode. The generated electrons are collected in the n-type region of the photodiode. Photo charge may be amplified when it moves from the initial charge accumulation region to the floating diffusion region or it may be transferred to the floating diffusion region via a transfer transistor. The charge at the floating diffusion region is typically converted to a pixel output voltage by the source follower transistor described above.
A portion of a CMOS pixel cell having a p-n-p photodiode 49 is illustrated in FIG. 2. A source follower transistor and row select transistor would be included in the 4-transistor (4-T) cell of FIG. 2, but are not shown in the depicted cross-section. A p+ region 21 is shown above an n-type region 23 to form the photodiode 49. Typically, the p+ region 21 is implanted to create a p-n junction. The illustrated pixel includes a transfer transistor with associated gate 26 and a reset transistor with associated gate 28, along with a floating diffusion region 16 and source/drain region 30. The illustrated pixel also includes shallow trench isolation (STI) regions 55.
Imagers having conventional pixel cells using p-n-p photodiodes often suffer from problems such as inefficient charge transfer and image lag due to potential barriers between the photodiode 49 and transfer gate 26 region. Fill factor loss is also a problem associated with conventional CMOS image sensors. Fill factor is a measure of the ratio of electrons produced per given light intensity. Fill factor loss may occur when higher concentrations of p-type dopants are used in the surface of a p-n-p photodiode and diffuse into n-type dopants, thereby compensating them and causing a reduction in fill factor.
Conventional pixel cells may also suffer from poor color fidelity, signal-to-noise ratios, and may not be able to operate over a wide range of lighting conditions. This is especially true with regards to blue response, i.e. the conversion of photons from blue wavelengths to an electrical charge. Because blue photons are absorbed closer to the surface and are, therefore, subject to surface defects and leakage, optimal color fidelity suffers as a result.